Transistor based devices used in microprocessors are commonly used to solve computational problems. As computational problems vary in size and complexity, scalability of such devices is a major concern. For example, non-deterministic polynomial complete problems (NP complete problems) are very difficult to solve. Providing solutions to such problems that involves today's technology, involves an exponential growth of computational steps and execution time, as the size and complexity of the problem grows.
Conventional hardware arrangements for providing computational solutions have been implemented with complementary metal-oxide semiconductor (CMOS) technology. Particularly, CMOS technology is used for constructing integrated circuits, such as microprocessors that employ transistors. CMOS systems have only linear improvements in speed and high power requirements. Thus, in handling complex problems, the linear nature of CMOS systems require multi-million core servers, which result in high power usage. To that end, CMOS systems are severely limited in scalability and power efficiency.
A software based computational method, such as the simulated annealing (SA) method, is another known approach to solving complex computational or optimization problems. However, the SA method, like other software based methods, have numerous inefficiencies associated with, for example, translating the software language to the Boolean based computing employed in existing technology. In addition, these software based methods are limited to existing known hardware, such as CMOS technology.
It is generally known that the scaling of transistor based devices used in microprocessors have many limitations, such as power dissipation, OFF state leakage, difficulty in miniaturizing metal interconnects, etc. In like manner, it is generally known that software based methods for providing computational solutions are limited due to their inefficiencies and reliance on hardware that have their own limitations.
A need therefore exists for hardware architecture that has the scalability to provide solutions to algorithms that have exponentially increasing complexity, and a method for implementing such hardware architectures.